New VLSI circuit architectures for addition and multiplication modulo (2/sup n/-1) and (2/sup n/+1) are proposed that allow the implementation of highly efficient combinational and pipelined circuits for modular arithmetic. It is shown that the parallel-prefix adder architecture is well suited to realize fast end-around-carry adders used for modulo addition. Existing modulo multiplier architectures are improved for higher speed and regularity. These allow the use of common multiplier speed-up techniques like Wallace-tree addition and Booth recoding, resulting in the fastest known modulo multipliers. Finally, a high-performance modulo multiplier-adder for the IDEA block cipher is presented. The resulting circuits are compared qualitatively and quantitatively, i.e., in a standard-cell technology, with existing solutions and ordinary integer adders and multipliers.

Efficient VLSI implementation of modulo (2/sup n//spl plusmn/1) addition and multiplication

Scan-based design for test (DFT) is a powerful testing scheme, but it can be used to retrieve the secrets stored in a crypto chip, thus compromising its security. On one hand, sacrificing the security for testability by using a traditional scan-based DFT restricts its use in privacy sensitive applications. On the other hand, sacrificing the testability for security by abandoning the scan-based DFT hurts the product quality. The security of a crypto chip comes from the small secret key stored in a few registers, and the testability of a crypto chip comes from the data path and control path implementing the crypto algorithm. Based on this key observation, the authors propose a novel scan DFT architecture called secure scan that maintains the high test quality of traditional scan DFT without compromising the security. They used a hardware implementation of the advanced encryption standard to show that the traditional scan DFT scheme can compromise the secret key. They then showed that by using secure-scan DFT, neither the secret key nor the testability of the AES implementation is compromised

Secure Scan: A Design-for-Test Architecture for Crypto Chips

Fault-based side-channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy-based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overheads (either area or performance). The authors investigate systematic approaches to low-cost low-latency CED techniques for symmetric encryption algorithms based on inverse relationships that exist between encryption and decryption at algorithm level, round level, and operation level and develop CED architectures that explore tradeoffs among area overhead, performance penalty, and fault detection latency. The proposed techniques have been validated on FPGA implementations of Advanced Encryption Standard (AES) finalist 128-bit symmetric encryption algorithms.

Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers

Scan-based design-for-test (DFT) is a powerful testing scheme, but it can be used to retrieve the secrets stored in a crypto chip thus compromising its security. On one hand, sacrificing security for testability by using traditional scan-based DFT restricts its use in privacy sensitive applications. On the other hand, sacrificing testability for security by abandoning scan-based DFT hurts product quality. The security of a crypto chip comes from the small secret key stored in a few registers and the testability of a crypto chip comes from the data path and control path implementing the crypto algorithm. Based on this key observation, we propose a novel scan DFT architecture called secure scan that maintains the high test quality of traditional scan DFT without compromising the security. We used a hardware implementation of the advanced encryption standard (AES) to show that the traditional scan DFT scheme can compromise the secret key. We then showed that by using secure scan DFT, neither the secret key nor the testability of the AES implementation is compromised.

/pdf/secure-scan-a-design-for-test-architecture-for-crypto-chips-1wn22trgzc.pdf

Secure scan: a design-for-test architecture for crypto chips

Recent dramatic improvements in integrated circuit fabrication technology have led to Field-Programmable Gate Arrays (FPGAs) capable of implementing entire digital systems, as opposed to the smaller logic circuits that have traditionally been targeted to FPGAs. Unlike the smaller circuits, these large systems often contain memory. Architectural support for the efficient implementation of memory in next-generation FPGAs is therefore crucial.
This dissertation examines the architecture of FPGAs with memory, as well as algorithms that map circuits into these devices. Three aspects are considered: the analysis of circuits that contain memory, as well as the automated random generation of such circuits, the architecture and algorithms for stand-alone configurable memory devices, and architectures and algorithms for the embedding of memory arrays in an FPGA.
We first present statistics gathered from 171 circuits with memory. These statistics include the number of memories in each circuit and the width and depth of these memories. We identify common interconnect patterns between memory and logic. These statistics are then used to develop a circuit generator that stochastically generates realistic circuits with memory that can be used as benchmark circuits in architectural studies.
Next, we consider the architecture of a stand-alone configurable memory that is flexible enough to implement memory configurations with different numbers of memories, memory widths and depths. Instrumental in this work is the algorithms that map memory configurations to the device. These algorithms are used in an experimental framework to investigate the effect of various architectural parameters on the flexibility, chip area, and access time of the configurable memory.
Finally, the architecture of an FPGA containing both embedded memory arrays and logic elements is considered, along with new automatic placement and routing algorithms that map circuits to the FPGA. We show that only 4 switches per memory block pin are required in the interconnection between the memory arrays and logic elements, and even lower in FPGAs with four or fewer memory arrays. In addition, we show that by providing direct connections between memory arrays, the FPGA density can be improved slightly, and the average memory access time can be improved by as much as 25%.

Architectures and algorithms for field-programmable gate arrays with embedded memory

A VLSI implementation of the International Data Encryption Algorithm is presented. Security considerations led to novel system concepts in chip design including protection of sensitive information and on-line failure detection capabilities. BIST was instrumental for reconciling contradicting requirements of VLSI testability and cryptographic security. The VLSI chip implements data encryption and decryption in a single hardware unit. All important standardized modes of operation of block ciphers, such as ECB, CBC, CFB, OFB, and MAC, are supported. In addition, new modes are proposed and implemented to fully exploit the algorithm's inherent parallelism. With a system clock frequency of 25 MHz the device permits a data conversion rate of more than 177 Mb/s. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols like ATM or FDDI. >

A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm

The authors describe VLSI architectures for multiplication modulo p, where p is a Fermat prime. With increasing p, ROM-based table lookup methods become unattractive for integration due to excessive memory requirements. Three novel methods are discussed and compared to ROM implementations with regard to their speed and complexity characteristics. The first method is based on an (n+1)*(n+1)-bit array multiplier, the second on modulo p carry-save addition, and the third on modulo (p-1) carry-save addition using a bit-pair recoding scheme. All allow very high throughputs in pipelined implementations. While the former is very convenient for CAD (computer-aided design) environments providing a pipelined multiplier macrocell, the latter two are well-suited to full-custom implementation. >

Regular VLSI architectures for multiplication modulo (2/sup n/+1)

A VLSI implementation of a novel secret-key block cipher is presented. Security considerations lead to novel system concepts in chip design including protection of sensitive information and failure detection capabilities. The VLSI chip implements data encryption and decryption in a single hardware unit. All important standardized modes of operation of block ciphers are supported. In addition, new modes are proposed and implemented to fully exploit the algorithm's inherent parallelism. With a system clock frequency of 25 MHz, this device permits a data conversion rate of more than 177 Mbit/s. The chip is the first silicon block encryption device that can be applied to on-line encryption in high-speed networking protocols like ATM (Asynchronous Transfer Mode) or FDDI (Fiber Distributed Data Interface). The high data throughput of 177.8 Mbit/s has been achieved by utilization of a sophisticated pipelining scheme and four full-custom modulo (2/sup 16/ + 1) multipliers. Two unidirectional high-speed 16-bit data ports guarantee continuous occupancy of the encryption unit.

VINCI: VLSI implementation of the new secret-key block cipher IDEA

Designers of VLSI circuits for cryptographic applications are faced with a severe dilemma: Concerns of security, requiring encapsulation of cryptographic applications, and testability, requiring access to all hardware subunits to check for their correct functionality, are basically contradictory. A further security requirement is the immediate detection of failure inside the encryption component. In this paper, an approach based on a compound system test strategy is introduced that reconciles the demands of security and testability. This system test strategy based upon built-in self-test on all levels of implementation allows off-line and concurrent checking without opening access to sensitive regions via test structures. The realization of the system test scheme is a new VLSI cipher implementation, VINCI, that fulfills all security demands for immediate failure detection and supports higher level system test strategies. >

VINCI: Secure test of a VLSI high-speed encryption system

The high speed architecture for a VLSI implementation of a new smart-key block cipher is presented. The chip performs data encryption and decryption in a single hardware unit. It runs with a maximum clock frequency of 33 MHz permitting a data conversion rate of more than 55 Mb/s. This high data rate, compared to currently available DES (data encryption standard) implementations, has been achieved by implementing a pipelined architecture and by using a sophisticated data scheduling scheme guaranteeing a continuously fully loaded pipeline. >

VLSI implementation of a new block cipher

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