A. Coppola
Cypress Semiconductor
16 Papers
136 Citations
A. Coppola is an academic researcher from Cypress Semiconductor. The author has contributed to research in topics: Logic synthesis & Routing (electronic design automation). The author has an hindex of 7, co-authored 16 publications. Previous affiliations of A. Coppola include Intel.
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Papers
A General Decomposition for Reversible Logic
Marek Perkowski,Lech Jozwiak,Pawel Kerntopf,Alan Mishchenko,Anas N. Al-Rabadi,A. Coppola,Andrzej Buller,Xiaoyu Song,Svetlana Yanushkevich,Vlad Shmerko,Malgorzata Chrzanowska-Jeske,Mozammel H. A. Khan +11 more
- 01 Jan 2001
TL;DR: This work presents for the first time a method that minimizes concurrently the number of gates, their total delay and the total garbage in reversible logic.
Regularity and Symmetry as a Base for Efficient Realization of Reversible Logic Circuits
Marek Perkowski,Pawel Kerntopf,Andrzej Buller,Malgorzata Chrzanowska-Jeske,Alan Mishchenko,Xiaoyu Song,Anas N. Al-Rabadi,Lech Jozwiak,A. Coppola +8 more
- 01 Jan 2001
TL;DR: The synthesis method to RPGAs allows to realize arbitrary symmetric function in a completely regular structure of reversible gates with smaller “garbage” than the previously presented papers.
Regular realization of symmetric functions using reversible logic
Marek Perkowski,Pawel Kerntopf,Andrzej Buller,Malgorzata Chrzanowska-Jeske,Alan Mishchenko,Xiaoyu Song,Anas N. Al-Rabadi,L. Jezwiak,A. Coppola,Bart Massey +9 more
- 04 Sep 2001
TL;DR: The synthesis method allows us to realize arbitrary symmetric function in a completely regular structure of reversible gates with relatively little "garbage" and is applicable to arbitrary multi-input multi-output Boolean functions.
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Board-level multiterminal net assignment for the partial cross-bar architecture
Xiaoyu Song,William N. N. Hung,Alan Mishchenko,Malgorzata Chrzanowska-Jeske,Andrew Kennings,A. Coppola +5 more
- 01 Jun 2003
TL;DR: A satisfiability-based method for solving the board-level multiterminal net routing problem in the digital design of clos-folded field-programmable gate array (FPGA) based logic emulation systems and shows that the method is time-efficient and applicable to large layout problem instances.
Segmented channel routability via satisfiability
TL;DR: This paper encodes the horizontal and vertical constraints of the routing problem as Boolean conditions and shows that the routability constraint is satisfiable if and only if the net connections in the segmented channel are routable.