K-nearest neighbour (KNN) is a supervised classification technique that is widely used in many fields of study to classify unknown queries based on some known information about the dataset. KNN is known to be robust and simple to implement when dealing with data of small size. However it performs slowly when data are large and have high dimensions. Therefore, KNN classifiers can benefit from the parallelism offered by Field Programmable Gate Arrays (FPGAs) to accelerate the algorithm. In addition, the KNN classifier is sensitive to the user defined parameter (K) which is the number of nearest neighbours. This parameter is known to affect the performance of the classifier; thus users would want the classifier to be easily adaptable to different values of K. In this work, we propose two adaptive FPGA architectures of the KNN classifier, and compare the implementations of each one of them with an equivalent implementation running on a general purpose processor (GPP). The proposed hardware implementations outperformed GPP by 76× for the first architecture and 68× for the second. In addition, we propose a novel dynamic partial reconfiguration (DPR) architecture of the KNN classifier, which allows for an efficient dynamic partial reconfiguration of a classifier implementation on FPGA for different K's. This DPR implementation offers 5× speed-up in the reconfiguration time of a KNN classifier on FPGA.

An adaptive implementation of a dynamically reconfigurable K-nearest neighbour classifier on FPGA

We designed a variety of k-nearest-neighbor parallel architectures for FPGAs in the form of parameterizable soft IP cores. We show that they can be used to solve large classification problems with thousands of training vectors, or thousands of vector dimensions using a single FPGA, and achieve very high throughput. They can be used to flexibly synthesize architectures that also cover: 1NN classification (vector quantization), multishot queries (with different k), LOOCV cross-validation, and compare favorably to GPU implementations. To the best of our knowledge this is the first attempt to design flexible IP cores for the popular kNN classifier.

Parallel architectures for the kNN classifier -- design of soft IP cores and FPGA implementations

Distance metric learning (DML) is successful in discovering intrinsic relations in data. However, most algorithms are computationally demanding when the problem size becomes large. In this paper, we propose a discriminative metric learning algorithm, develop a distributed scheme learning metrics on moderate-sized subsets of data, and aggregate the results into a global solution. The technique leverages the power of parallel computation. The algorithm of the aggregated DML (ADML) scales well with the data size and can be controlled by the partition. We theoretically analyze and provide bounds for the error induced by the distributed treatment. We have conducted experimental evaluation of the ADML, both on specially designed tests and on practical image annotation tasks. Those tests have shown that the ADML achieves the state-of-the-art performance at only a fraction of the cost incurred by most existing methods.

A Distributed Approach Toward Discriminative Distance Metric Learning

The implementation of face recognition techniques in an embedded system is a very important aspect of various security applications, such as authorization identification in cash machines and door access for employee attendance. The purpose of this paper is to survey the existing hardware implementations of a face recognition system, particularly those who used for developing an embedded door access control system. This includes a brief discussion about face recognition algorithms and the hardware platforms outlining the importance of using a Field Programmable Gate Array (FPGA) device, which can be used to design an embedded door access control system. It is found that the success of any door access control system depends on the type of face recognition algorithm in the feature extraction phase of the face recognition system and the selected hardware device. Based on a comparison between different feature extraction algorithms, the use of a hybrid feature extraction technique can improve the accuracy of face recognition system. An efficient door access control system can be obtained using a FPGA device, which is preferable because of its technical characteristics of parallelism, re-programmability and very high speed, in the implementation of a face recognition system.

Embedded door access control systems based on face recognition: A survey

Bio-inspired computer vision is an emerging field. It aims to reproduce the capabilities of biological vision systems, eventually to simulate the visual functions for various purposes. In this paper, we propose a bio-inspired computer visual system using Graphical Processing Unit (GPU), and its application on breast cancer prognosis. The system extracts visual features from an input image using a mechanism which is similar to human visual system. Then classify the visual features using a machine learning algorithm. As a result, the elements of the input image, which might be related to particular knowledge concepts, can be identified.

Bio-inspired computer visual system using GPU and Visual Pattern Assessment Language (ViPAL): Application on breast cancer prognosis

This paper discusses the suitability of reconfigurable computing to speedup classification problems using the nearest neighbour (1NN) classifier. INN classifier is widely used in the literature especially in real-time applications such as face recognition, on-line hand-written character recognition and medical applications where the performance enhancement in terms of speed is desirable. To evaluate the effectiveness of our implementation on field programmable gate arrays (FPGAs), experiments were carried out on two medical data sets. Results have shown that the classification accuracy is exactly same for both FPGAs and microprocessor (muP) based solutions with FPGA has superior speed performances

An Fpga Based Coprocessor for Cancer Classification Using Nearest Neighbour Classifier

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An Fpga Based Coprocessor for Cancer Classification Using Nearest Neighbour Classifier