Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

/pdf/fundamentals-of-modern-vlsi-devices-471xd7l9pf.pdf

Fundamentals of Modern VLSI Devices

Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.

CMOS scaling into the nanometer regime

https://engineering.purdue.edu/~ee650/downloads/NBTI-Ref1.pdf

A comprehensive model of PMOS NBTI degradation

High-k gate dielectrics, particularly Hf-based materials, are likely to be implemented in CMOS advanced technologies. One of the important challenges in integrating these materials is to achieve lifetimes equal or better than their SiO/sub 2/ counterparts. In this paper we review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results. High-k materials show novel reliability phenomena related to the asymmetric gate band structure and the presence of fast and reversible charge. Reliability of high-k structures is influenced both by the interfacial layer as well as the high-k layer. One of the main issues is to understand these new mechanisms in order to asses the lifetime accurately and reduce them.

Review on high-k dielectrics reliability issues

We present a new direct VT measurement technique with arbitrary choice of drain voltage and a mus delay (factor of 1000 improvement) after stress. As shown this technique enables a meaningful comparison of data to theory (e.g. DeltaVT measurable as response to stress times from 100mus over 10 decades in time and an analysis of recovery over 11 decades in time) which may lead to a better understanding of NBTI. A fast precursor due to bulk trapping was found to significantly influence degradation slopes for all times. Based on a physical model - standard reaction/diffusion model plus fast bulk trapping -with just 3 fit parameters experimental degradation can be well modelled and degradation slopes frac14 (both reported in literature) can be explained. A lifetime extrapolation based on this physical model is superior to the common straight line fit. There is no satisfying agreement of recovery data with reaction/diffusion theory. Further experimental and theoretical work is going to be needed

Analysis of NBTI Degradation- and Recovery-Behavior Based on Ultra Fast VT-Measurements

In this work the reliability of a 0.35 /spl mu/m p+ poly-gate pMOSFET CMOS technology under conductive channel hot carrier conditions is investigated. It is found that at any bias and temperature condition applied, the degradation of sufficiently short channel length (Leff/spl sime/0.14 um) devices results in a reduction in drive current due to the impact of donor type interface trap generation and positive charge formation during the stress. At these dimensions the degradation is controlled by a contribution of both Negative Bias Temperature Instability (NBTI) and Channel Hot Carrier (CHC) mechanism. We will show the role that each of these two mechanisms play in determining the shift of typical device parameters. A methodology to decouple the two effects is also provided allowing to quantify each contribution separately at any bias and temperature condition. A conductive CHC model that takes into account the impact of both mechanisms to the device lifetime at the worst observed degradation condition (Vg=Vd) is also discussed.

NBTI-channel hot carrier effects in PMOSFETs in advanced CMOS technologies

We demonstrate a 0.08 /spl mu/m CMOS suitable for high-performance (V/sub dd/=1.8 V) and low-power applications (V/sub dd/<1.5 V) with the best current drive at a given off-current reported in the literature to date. Excellent short-channel effects were obtained for L/sub eff/ down to 0.06 /spl mu/m in the NFET and 0.08 /spl mu/m in the PFET. Aggressive lateral and vertical dopant engineering allow the VT to be reduced with no degradation in short-channel effects resulting in a 50% improvement in delay at V/sub dd/=1 V over the regular-V/sub T/ process.

A high-performance 0.08 /spl mu/m CMOS

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NBTI-channel hot carrier effects in PMOSFETs in advanced CMOS technologies

A high-performance 0.08 /spl mu/m CMOS